The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a complementary type semiconductor device having a well in a surface region thereof.
In order to achieve micro-patterning of a complementary type semiconductor device such as a CMOS, a well isolation technique must be established. This is because most drawbacks of the CMOS transistor are associated with well isolation. For example, serious problems occur such as a decrease in a breakdown voltage between a P.sup.+ -layer and a P-well (or an N.sup.+ -layer and an N-well) upon scaling a device, a decrease in a latch-up breakdown voltage due to the thyristor effect, an increase in a chip area in accordance with well isolation, and the like.
A conventional CMOS transistor is manufactured in the following manner. Referring to FIG. 1, a P-well 2 and an N-well 3 are formed in a surface region of a P-type semiconductor substrate 1 by a known method, and thereafter, a groove 4 which reaches the substrate 1 is formed between the wells 2 and 3. The surface of the resultant structure is oxidized and a polycrystalline silicon layer is deposited on the overall surface thereof. The polycrystalline silicon layer is etched so as to leave it only in the groove 4. The polycrystalline silicon layer in the groove 4 is oxidized, thereby forming an insulating oxide film 5. Gate electrodes 6 and 7 are respectively formed on the P-well 2 and the N-well 3 through insulating films 8 and 9 by a known method. An N-type impurity is doped in the P-well 2 using the gate electrode 6 as a mask so as to form source and drain regions 10 and 11. In the same manner, a P-type impurity is doped in the N-well 3 using the gate electrode 7 as a mask so as to form source and drain regions 12 and 13. Thereafter, an intervening insulating film 14 is formed on the overall surface of the resultant structure, and contact holes 15 corresponding to the respective source and drain regions are then formed. Interconnection wiring 16 is formed to be connected to a Vss terminal (power line) through the contact hole 15 corresponding to the source region 10 of the P-well 2. Interconnection wiring 17 is formed to be connected to a Vcc terminal (power line) through the contact hole 15 corresponding to the source region 12 of the N-well 3. Furthermore, interconnection wiring 18 is formed to connect the drain regions 11 and 13 of the P-and N-wells 2 and 3 through the corresponding contact holes 15, thus obtaining a CMOS transistor.
In the CMOS transistor manufactured in this manner, isolation between the P- and N-wells 2 and 3 is performed by the insulating oxide film 5 buried in the groove 4. For this reason, a breakdown voltage between the P.sup.+ -type drain region 13 and the P-well 2 (or between the N.sup.+ -type drain region 11 and the N-well 3) is determined by a distance between the drain region 13 (or drain region 11) and the P-type substrate 1 and is considerably improved. Since a lateral PNPN structure is divided by the oxide film 5, the thyristor effect can be prevented, thus improving a latch-up breakdown voltage. In this case, it should be noted that in order to prevent the latch-up phenomenon, the substrate 1 or the P-well 2, and the N-well 3 must be sufficiently biased by Vss and Vcc voltages. For this reason, in the transistor shown in FIG. 1, the Vss and Vcc terminals are formed on the insulating film 14, and Vss and Vcc voltages bias the P- and N-wells through the contact holes formed in the insulating film 14. However, in an arrangement of, e.g., a memory cell, if the Vss and Vcc terminals are provided in a portion of high density layout, the contact holes are formed therein, and Vss and Vcc voltages bias the P- and N-wells 2 and 3 through these terminals and contact holes, micro-patterning of the device is prevented.
In another prior art example, as shown in FIG. 2, a CMOS transistor has a structure in which the N.sup.+ -type drain region 11 of the P-well 2 and the P.sup.+ -type drain region 13 of the N-well 3 are formed to be in contact with the insulating oxide film 5. In the transistor with such a structure, since the drain regions 11 and 13 are formed to be in contact with the insulating oxide film 5, the area of a boundary portion between the P- and N-wells 2 and 3 can be decreased and a capacitance at side surfaces of the drain regions 11 and 13 can be reduced. However, in the CMOS transistor shown in FIG. 2, a leakage current undesirably flows through the contact surfaces between the insulating oxide film 5 and the drain regions 11 and 13. This is a serious drawback in the CMOS transistor which has a feature of low power consumption.